In Japanese Patent Application Laid-Open Publication No. 2005-116744 (Patent Document 1), a technology of forming a high voltage resistant transistor and a low voltage resistant transistor on a same substrate is described. In this Patent Document 1, it is said that the high voltage resistant transistor has an offset insulating layer for relaxing an electric field. A guard ring formed in the high voltage resistant transistor formation region is connected to a wire (a wire of the lowest layer) formed on an interlayer insulation film of the first layer. In contrast, a source region or a drain region of the high voltage resistant transistor is connected to a wire (not the wire of the lowest layer) formed on an interlayer insulation film of a second layer. In other words, the source region or the drain region of the high voltage resistant transistor is connected to a wire arranged on the interlayer insulation film of the second layer by a plug that penetrates both the interlayer insulation film of the first layer and the interlayer insulation film of the second layer at once.
In Japanese Patent Application Laid-Open Publication No. 4-171938 (Patent Document 2), a technology of forming a high voltage resistant n-channel FET and a low voltage resistant n-channel FET on a same substrate is described. In this Patent Document 2, in the low voltage resistant n-channel FET, a source region or a drain region thereof is connected to a wire of the lowest layer formed on an interlayer insulation film of the first layer. In contrast, in the high voltage resistant n-channel FET, a source region or a drain region thereof is connected to, not the wire of the lowest layer, but a wire formed on an interlayer insulation film of a second layer.